'Design of Chip Security' is a 54-hour advanced-level course within the 'Hardware Security Tutorial Series'. It covers the introduction of standard IC design processes applied in the industry and includes hands-on practices using FPGA development boards for secure chip design, testing, and verification. Prior completion of the intermediate course 'Introduction to Hardware Security' is recommended. This course involves extensive hands-on work, and participants will use:

1. C language

2. Linux instructions

3. Verilog

4. EDA Tool

The course is offered at the National Tsing Hua University (NTHU), and taught by Dr. Meng-Yi Wu, Director of R&D at PUFsecurity. Students who register with NTHU will receive an FPGA board for hands-on projects. The course provides practical insights into IC design processes and includes using hardware languages and EDA tools for crypto engine design, testing, and verification.

Course Schedule

According to the National Tsing Hua University calendar, the course is offered in the second semester of each academic year, typically starting in February

Registration:

Due to limited course capacity, submitting a resume is required for enrollment. Students will be admitted and provided with learning suggestions and materials until full admission.

Recommended Prior Knowledges

• C language & Binary oparation

• Electronics (basic RLC & MOSFET concepts)

• Logic gates (AND, OR, XOR, etc.)

• Fundamentals of logic circuit (Multiplexer, Comparator, Counter, etc.)

In this course, you will learn:

• Hardware Root of Trust (RoT) use cases

• Security design for System-on-Chip (SoC)

• Standard processes of IC design

• Digital logic design syntax

• Design rules and coding styles adhered to in the IC design industry

• Ability for developing cryptographic engines

This course covers:

Chapter 1 Introduction to Chip Security

　　• Hardware Root of Trust

　　• Secure Enclave

　　• Protocol and Certificate

　　• Secure Boot

Chapter 2 Logic Circuit Design Part I

　　• Linux Instructions

　　• RTL Instructions

　　• Combinational Logic

　　• Sequential Logic

Chapter 3 Mini Project: Combinational & Sequential circuit

Chapter 4 Logic Circuit Design Part II

　　• Finite State Machine

　　• TestBench

Chapter 5 Mid-term Project: Crypto Engine Synthesis

Chapter 6 Circuit Verification and Demonstration

　　• Design from Code to Chip

　　• EDA Tool

　　• Intorduction to FPGA environment

Chapter 7 Final Project: Verification & Demonstration